This invention relates generally to semiconductor devices of the metal-oxide-silicon (MOS) type and to the production or fabrication of integrated circuits containing arrays of such devices. More particularly, the present invention relates to an improved method for fabricating complementary or CMOS type integrated circuits.
In conventional CMOS devices which use opposite polarity transistors to perform circuit functions, an important step in the fabrication process is the formation of lightly-doped areas of P-type diffusion, or "P-wells", within which the N-channel transistors are formed. These relatively deep P-well diffusions are normally formed at a low doping level and require extreme precision since the dopant concentration regulates both the threshold voltage V.sub.T and the breakdown voltage of the N-channel MOSFET's. The formation of the P-wells is further complicated by the fact that in any integrated circuit array, parasitic transistors are created by conductive interconnect lines that extend over the field oxide areas. If the field oxide is thin enough to allow inversion, parasitic leakage can occur that could cause the circuit to malfunction or use excessive power. To overcome this problem, it was heretofore necessary to increase the field oxide thickness in the field area to several times the oxide thickness in the device area. For example, in prior art CMOS circuits, the field oxide to device oxide ratio was often required to be 15 to 1 or greater. A serious disadvantage with this requirement for a relatively thick field oxide was that it created large oxide step heights and limited the use of fine line geometrics in CMOS integrated circuits.
In addition to the aforesaid requirement for a relatively thick field oxide and the inherent "step" problems, a further disadvantage with prior CMOS integrated circuits was that they also required "channel stop" diffusions to provide isolation and prevent leakage between transistor cells. Although such channel stops did not require extra processing steps, they did require extra area and thus substantially increased the size of the integrated circuit chip.
The present invention, as described herein, solves both of these problems with a fabrication process using field implants which removes the requirement for channel stops and also allows a thinner field oxide layer to be used. This improvement provides better thin film step coverage and easier, more efficient photolithography which in turn allows fine line widths and small spaces in the overall circuit topography, thereby making possible a smaller chip size for the circuit.
Yet another problem encountered with prior methods for fabricating CMOS devices with isolated P-wells was that a reduction of doping concentration inherently occurred at the edges of the P-wells under the field oxide at the exact location where the dopant was most needed. This doping reduction occurred because of the typical diffusion distribution which normally causes less dopant at the edges of a diffusion area and also the fact that field oxide has a tendency to deplete dopant at the silicon/oxide interface. Also, in prior CMOS processes, P-wells were formed by ion implantation using field oxide regions already formed as the implant barriers. This often resulted in an array having adjacent P-wells which were isolated from each other unless located closely together, an arrangement that required more topside contacts and therefore more chip area. One method previously suggested for alleviating this problem was to increase the P-well sidewall doping by increasing the original P-doping level and thereafter counterdoping with an N-type dopant. However, this approach proved to be unsatisfactory because it degraded majority carrier mobility and increased N+ area capacitance and hence reduced N-channel device performance. These problems are also solved by the prsent invention.
Accordingly, a general object of the invention is to provide an improved method for making CMOS integrated circuit devices that solves the aforesaid problems.
Another object of the invention is to provide a method for fabricating CMOS semiconductor devices that greatly reduces the ratio of field oxide to device oxide thickness and this eliminates relatively large steps for the conductive paths of the device.
Yet another object of the invention is to provide a method for fabricating CMOS semiconductor devices that provides a deeper and more concentrated doping level along the edges of each P-well extending under the edges of adjacent field oxide areas.
Another object of the invention is to provide an improved CMOS structure that provides a relatively small ratio of field oxide to device oxide thickness and thereby enables the use of relatively narrow conductive interconnect lines.
Another object of the invention is to provide an improved CMOS integrated circuit device structure wherein a single P-well diffusion area is utilized for adjacent N-type transistors of two or more CMOS elements.
Another object of the invention is to enable the reduction of field oxide thickness which reduces the height of oxide steps which subsequent thin film layers must traverse.